Idea!'s Microelectronics Business Unit focuses on the development of Digital Signal Processing (DSP) ASIC IP cores in both RTL and GDS forms for high-speed optical transceivers. The IP cores cover many application fields from short reach data center interconnects (DCI), WDM metropolitan to long-haul systems at speeds 100G, 200G, 400G and beyond per wavelength.
The highly integrated IP cores bring the best in power consumption optimization, area reduction and system performance following a continuous integration and streamlined ASIC development flow with front-end design, universal verification methodology, automatized back-end design and sign-off.
- Optical system modeling including data center interconnects, WDM metropolitan and long-haul
- Digital signal processing architecture in floating and fixed-point with cycle accuracy for coherent optical systems and common electrical interfaces (CEI)
- Register Transfer Level (RTL) design and simulation with very early power estimation and system validation
- Logic/physical synthesis to estimate power consumption at gate level and anticipate ASIC layout
- RTL and Gate-Level cooperative Verification following universal verification methodology with push-bottom regressions
- Reference Back-End design flow in compliance with EDA vendor and Foundry guidelines including
- Floorplan with chiptop integration (digital and analog)
- Place and Route with clear audit checks
- Physical Verification: STA, DRC/LVS and IRDrop/EM
- Streamlined IT infrastructure in the cloud to seamlessly support tape-out peaks!
- DSP-IP in RTL form
- DSP-IP core in GDS form for Common Electrical Interfaces
- DSP-IP in GDS form for highly optimized power consumption optical interfaces
- DSP-ASIC low cost for short-reach, WDM metro and Long-Haul