Soft Cores e IPs

In the list of recent IPs developed by IDEA! Electronics, there are IPs both for the detection and correction of errors, encoders, interleavers, among which are cited:

  • Reed-Solomon encoder;
  • LDPC encoder;
  • BCH encoder.


Reed-Solomon Encoder:

Correction codes of Reed-Solomon are widely used in telecommunications and data storage, such as:

  • Mass storage devices: CDs, DVDs, etc;
  • Wireless Communication: TV Digital Terrestrial (ISDB), cellular, links, microwave oven;
  • Communications via Satellite: Digital TV (DVB-S);
  • High Speed modens : ADSL, xDSL, etc..

This encoder is compatible with G709 standards DVB-S1, ISDB-T and others that use it in their FEC mechanisms (foward error correction); it can also be used with the shortned codes (255, 239) or (204, 188) .

In order to provide reduction in area, still has great performance, allowing an exit per cycle and working at a rate of over 250Mhz in fpgas of Stratix II family.


Low-density parity-check encoder (LDPC):

Turbo encoders as LDPC are what's latest in correction of errors in digital applications. Despite its innovative use, the design of these algorithms dates from the 60's, but their effective use was only possible after the decade of 90 due to the volume and complexity of their calculations.

Currently it is already used in the second generation of the European Digital-TV standard (DVB-S2, DVB-T2) and wireless networks WiMAX (IEEE 802.16)

The developed soft-IP is compatible with DVB-S2 standard and works in the rates of 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, 8 / 9, 9 / 10.

It has two different architectures, optimized for area or performance. Both with the excellent throughput, spending from 1.1 to 0.5 cycles for each generated data . This performance is possible thanks to an internal pipeline of 9 stages, which can perform 8 operations per cycle.

BCH Encoder (Bose-Chaudhuri-Hocquenghem):

The BCH is a multi-level correction code. It's cyclical and variable in size and it's used to correct the insertion of random errors. It is from the same family as Reed-Solomon and also widely used in FEC mechanisms (foward error correction).

This soft-IP is compatible with the pattern DVBS2, among others. It is capable of processing 1 bit per cycle, working at frequencies above 200Mhz when in FPGAs.